The present invention relates to a method for manufacturing a highly integrated semiconductor device, and particularly to a method for manufacturing memory cells for DRAMs (dynamic random access memories).
The decrease in cell capacitance accompanying reduction in the memory cell area is a serious hindrance to increasing the packing density of a DRAM, as it causes a degraded read-out capability and an increase in the soft error rate of the memory cell as well as consuming excessive power during low voltage operation by impeding device operation. Thus, increasing the cell capacitance by ensuring adequate unit area is essential along with increasing the packing density.
Generally, in a 256 Mbit DRAM having a 0.25 .mu.m.sup.2 design rule, when employing a two-dimensional structure staked memory cell, sufficient cell capacitance cannot be obtained even though a high dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5) is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to increase cell capacitance. The double stack, fin, spread stack, and cylindrical electrode structures are all proposed for a storage electrode having a three-dimensional structure to increase the cell capacitance of a memory cell.
Since both the outer and inner electrode surface can be utilized as an effective capacitor area, the cylindrical structure is favorably adopted as a three-dimensional stacked capacitor, and is suitable for an integrated memory cell circuit which is 64 Mb or higher in capacity. However, the simple cylindrical structure cannot provide sufficient cell capacitance for a highly integrated memory cell which is 256 Mb or higher in capacity. Therefore, various new structures have been suggested to increase cell capacitance by improving the above cylindrical structure.
The CROWN cell structure, suggested by Toru Kaga in 1991, increases the cell capacitance by forming the cylindrical electrode as a crown-shape electrode having a double-wall structure (IEEE Transactions on Electron Device '91, "Crown-Shaped Stacked-Capacitor Cell for 1.5 V Operation 64 Mb DRAMs").
FIGS. 1 through 3 are cross-sectional views for illustrating the method for manufacturing the above-mentioned CROWN cell.
Referring to FIG. 1, a pair of transistors each having a source region 14 and a gate electrode 18, and commonly sharing a drain region 16 and a bit line 20 in contact with drain region 16 are formed on an active region of a semiconductor substrate 10 which is divided into active and isolation regions by a field oxide 12. Then, an insulating layer 19 is formed on the entire surface of the resultant structure for insulating the transistor. After forming a planarizing layer 30 for planarizing the surface of substrate 10, an etch-blocking layer 31, e.g., a silicon nitride (Si.sub.3 N.sub.4) layer is formed on planarizing layer 30. Then, etch-blocking layer 31, planarizing layer 30, and insulating layer 19 are partially etched, thereby forming a contact hole for connecting a storage electrode of a capacitor to source region 14. Thereafter, a conductive material, e.g., an impurity-doped polysilicon is deposited and etched back, to thereby form a bottom electrode 50. Then, an oxide, e.g., a silicon dioxide (SiO.sub.2) is thickly deposited and patterned to form an oxide film groove 32. Thereafter, a conductive material, e.g., an impurity-doped polysilicon is deposited, to thereby form a first conductive layer 50A which is connected with bottom electrode 50. Then, an oxide, e.g., a silicon dioxide for forming a cylindrical electrode portion of the storage electrode is deposited and etched anisotropically, to thereby form an oxide film spacer 33 on a side of first conductive layer 50A. After depositing a conductive material, e.g., an impurity-doped polysilicon to form a second conductive layer 52, an oxide, e.g., a silicon dioxide is deposited and etched back, thereby filling the oxide 34 the within oxide film groove 32. Here, due to the presence of oxide 34, second conductive layer 52 is prevented from being removed during a subsequent etching process.
Referring to FIG. 2, first and second conductive layers 50A and 52, which exist in the portions except in the interior of oxide film groove 32, are etched back to form cylindrical electrodes 50a and 52a isolated from each other. Here, because cylindrical electrodes 50a and 52a are formed by etching first and second conductive layers 50A and 52 which exist between oxide film groove 32, oxide film spacer 33, and oxide 34, are formed with sharp portions P at the top edges of the cylindrical electrodes. Sharp portions P cause leakage currents and the breakdown of the dielectric layer, and thus degrade the reliability of the device.
Referring to FIG. 3, the oxide film groove 32, oxide film spacer 33 and oxide 34 are all removed by a wet etching process using etch-blocking layer 31 as an etch-end point, so that a storage electrode 100 composed of bottom portion 50 and cylindrical portions 50a and 52a is formed. Thereafter, a dielectric layer 110 is formed over the entire surface of storage electrode 100, and a conductive material, e.g., an impurity-doped polysilicon is deposited to form a plate electrode 120. As a result, capacitors C1 and C2 each composed of storage electrode 100, dielectric layer 110, and plate electrode 120 are completed.
In the highly integrated memory cell, the distance between neighboring capacitors must be reduced so as to necessitate an increase in cell capacitance by maximizing the area of capacitor. According to the above-described conventional method, since the distance between neighboring capacitors (refer to A in FIG. 3) is determined by the pattern size of the photoresist, it cannot be minimized to a value smaller than the limitation imposed by the lithographic technique employed. Therefore, the capacitor area cannot be maximized, and thus the desired cell capacitance cannot be obtained.
A capacitor which is disclosed in European Patent Publication No. 404,553 A1, is manufactured so as to overcome the above-described problem. The method for manufacturing the above-mentioned capacitor will be explained with reference to FIG. 4 and FIG. 5.
Referring to FIG. 4, after forming the contact hole which exposes source region 14 of the transistor by the method as already described with reference to FIG. 1, a conductive material, e.g., an impurity-doped polysilicon is deposited to a constant thickness on the base of etch-blocking layer 31 and fills the contact hole completely, to thereby form a first conductive layer 50. Thereafter, for example, a phosphor-silicate glass (PSG) film is coated on the entire surface of the resultant structure and etched anisotropically, to thereby form a first oxide film spacer 36 on the side of the PSG film pattern. Then, the PSG film pattern is removed, and first conductive layer 50 is etched to a predetermined depth, using first oxide film spacer 36 as an etch-mask. Thus, a thin conductive film 50b and cup-shaped electrode 50a are formed.
Referring to FIG. 5, an oxide, e.g., a silicon dioxide is deposited on the entire surface of the resultant structure and etched anisotropically, to thereby form a second oxide film spacer (not shown). Then, a conductive material, e.g., an impurity-doped polysilicon is deposited to form a second conductive layer (not shown), and the second conductive layer and first conductive layer are etched anisotropically, using etch-blocking layer 31 as an etch end-point. As a result, cup-shaped principle electrode 50a, ring-shaped peripheral electrode 52 and bottom electrode 50 which connects principle electrode 50a with peripheral electrode 52 are formed. Thereafter, a dielectric film 110 is formed by coating a high dielectric material on the entire surface of the resultant structure, and a plate electrode 120 is formed by depositing a conductive material, e.g., an impurity-doped polysilicon, so that a capacitor composed of storage electrode 100, dielectric film 110 and plate electrode 120 is completed.
According to the conventional method described above, since the peripheral electrode 52 is formed in self-aligned fashion with the principle electrode 50a, the distance between neighboring capacitors (refer to A' in FIG. 5) can be minimized to a value smaller than the limitation imposed by the lithographic technique, thereby maximizing the area of the capacitor. On the other hand, it is difficult to form the thin conductive film (refer to 50b in FIG. 4) connecting peripheral electrode 52 with principle electrode 50a. The thin conductive film 50b is formed by etching the first conductive layer (refer to 50 in FIG. 4) to a predetermined depth. Since it is impossible to detect an etch end-point during the above etching process, the stability of the process cannot be assured.